Unless otherwise indicated, the foregoing is not admitted to be prior art to the claims recited herein and should not be construed as such.
When a field effect transistor (FET) device switches between the ON state and the OFF state, charge built up in the gate redistributes across the source and drain terminals. This typically manifests itself as an extraneous signal in the output (e.g. at the drain terminal), which is sometimes referred to as switching glitch. The switching glitch in a FET device is proportional to
      ⅆ    i        ⅆ    t  of the device, where i is the drain current.
Referring to FIG. 9, for example, in a typical driving scheme for a PMOS device M where the gate drive signal VGS is a linearly rising signal,
      ⅆ          I      d            ⅆ    t  during saturation is high, which can result in a large glitch. The device M typically will drive a load with a driving signal Drv_p. A driver may be used to boost or otherwise buffer the driving signal Drv_p (typically a small signal) so that the driving signal can operate the device M. As can be seen in FIG. 9, switching glitches can arise from the parasitic influences (e.g., parasitic capacitances Cpar, parasitic inductances Lpar from the load, the wire routing, and so on) when device M switches from the OFF state to the ON state. In particular, the parasitic inductance and capacitance can create a sharp ringing voltage during the turning-on process of the switch, referred to as “switching glitch.” When the device M is a switching element in a high power application such as a negative charge pump, a voltage regulator (e.g., buck regulator, boost regulator, etc.), a class D amplifier, and so on, the switching glitches can be significant.
FIG. 10 shows the drain current Id profile as the gate drive voltage VGS increases. Operation of the an FET device is typically characterized by three operating regions (also shown in FIG. 10): region 1 (OFF or cutoff region), the device is non-conductive; region 2 (saturation region), the drain current Id flowing from the drain to the source of the FET transistor is the highest for the gate-source voltage VGS that is supplied; and region 3 (linear or ohmic region), where the device operates like a resistor.